基本要求：
- 电子工程或相关专业硕士
Master’s in EE and related fields
- 熟练使用电路设计工具，版图设计工具以及SPICE仿真工具
Experience with tools for schematic entry, IC layout and SPICE simulation
- 熟练使用Verilog-A语言对模拟电路进行行为级建模和仿真
Knowledgeable in Verilog-A for analog behavioral modeling and simulation-control/data-capture
- 有使用TCL，Perl，C，Python，MATLAB或其他脚本语言的经验
Experience with TCL, perl, C, python, MATLAB, or other scripting languages
- 英文通过六级，有一定听说写能力
Language proficiency over level 6 and listening, writing and reading can meet basic daily working requirements

岗位关键词：
- 使用最先进的工艺（如7nm/10nm）开发创新型模拟与混合集成电路
Design innovative analog and mixed-signal integrated circuits based on advanced technology (like 7nm/10nm)
- 与全球具有不同技术背景的模拟/数字电路设计工程师协同工作
Work with a cross functional design team of analog and digital designers from a wide variety of backgrounds
- 从事与模拟混合信号相关的IP设计
involve related to analog design and mixed signal IP design
- 基于CMOS器件的电路设计，开发随机存储器及版图
Circuit Design, SRAM, Layout